1. Field of the Invention
The present invention relates to a clock gating circuit capable of blocking a clock supplied in an active mode when a device in a targeted logic circuit does not operate and retaining data without leakage current in a sleep mode, by using a Multi-Threshold CMOS (MTCMOS) technique.
The present invention has been produced from the work supported by the IT R&D program of MIC (Ministry of Information and Communication)/IITA (Institute for Information Technology Advancement) [2006-S-006-01, Components/Module technology for Ubiquitous Terminals] in Korea.
2. Discussion of Related Art
FIG. 1 illustrates a conventional clock gating circuit using a single threshold voltage and including an AND gate 150. A gated clock GCLK is transferred to a flip-flop 200. When an enable signal EN is high, an input clock CP passes through the AND gate 150 and the gated clock GCLK is transferred to the flip-flop 200. When the enable signal EN is low, the gated clock GCLK becomes low irrespective of the input clock CP and the clock is not supplied to the flip-flop 200. Thus, the clock gating circuit has such a simple structure. However, the gated clock GCLK from the clock gating circuit of FIG. 1 may include glitch or spike.
FIG. 2 illustrates a clock gating circuit 160 comprising a latch circuit located at an input of the AND gate 150 to solve the problem associated with the clock gating circuit of FIG. 1, in which a conventional single threshold voltage is used. Here, when a 130 nm transistor operating at 1.2V is used, the single threshold voltage is about 0.34V. The configuration and operation of the conventional clock gating circuit of FIG. 2 will now be described. The clock gating circuit 160 using a single threshold voltage includes a transmission gate 100 that is controlled by a clock signal CP and an inverted clock signal CPb and receives an enable signal EN from a targeted logic gate 170, a feedback transmission gate 140 connected via a second inverter 130 for inverting an output signal of a first inverter 110, and an AND gate 150 for receiving the enable signal from the third inverter 120 via the first inverter 110 and the clock CP and outputting the gated clock GCLK.
The clock signal CP is generated by a clock signal generating circuit (not shown), and the inverted clock signal CPb is an inverted version of the clock signal CP.
Each of the transmission gate 100, the inverters 110, 120 and 130, the feedback transmission gate 140, and the AND gate 150 consists of a PMOS transistor and an NMOS transistor each having a single threshold voltage, i.e., an intermediate threshold voltage (normal Vt), as shown in FIGS. 3a and 3b. 
Operation of the clock gating circuit of FIG. 2 will now be described.
When the clock signal CP is high and the inverted clock signal CPb is low, the transmission gate 100 is turned on and the feedback transmission gate 140 is turned off.
In this case, when the enable signal EN is high, the output signal passing through the first inverter 110 and the third inverter 120 becomes high and is input to the AND gate 150. The clock signal CP at a high level is also input to the AND gate 150. Accordingly, the gated clock GCLK becomes high to turn the targeted logic circuit 170 on.
On the other hand, when the enable signal EN is low, the output signal passing through the first inverter 110 and the third inverter 120 becomes low and is input to the AND gate 150. The clock signal CP at a high level is also input to the AND gate 150. Accordingly, the gated clock GCLK becomes low to turn the targeted logic circuit 170 off and block the clock.
When the clock signal CP is low and the inverted clock signal CPb is high, the transmission gate 100 is turned off and the feedback transmission gate 140 is turned on. Accordingly, the clock gating circuit enters a standby state and retains a previous data state in the feedback circuit.
Although a conventional clock gating circuit comprising a single threshold voltage can block the clock when a specific targeted circuit is not active, it is difficult to implement a high-performance and low-power circuit due to leakage current in a scaled-down device.